8th IEEE

Workshop on Intelligent Solutions in Embedded Systems
(Heraklion, Crete, Greece, 8-9 July 2010)

Welcome to WISES2010

Dear Colleagues,

We are proud and excited to announce the Technical Programme of WISES2010.
The objective of the WISES2010 workshop is to provide a presentation forum for innovative approaches dealing with intelligent solutions in embedded systems, fostering and sharing the exchange of original ideas and best practices among researchers, practitioners, and application developers from industry and academia. Papers describing simulation and modeling tools, platform implementations and prototype deployments of embedded systems are particularly welcome.
Topics of interest included:
Embedded systems architecture,
Software for single or multi-core embedded systems,
Prototype platforms, applications and case studies, and
Tools and methodologies for analysis, exploration and validation.
We wish for a scientifically exciting and productive WISES2010 event.

Organizing Committee, WISES2010
Miltos Grammatikakis, George Kornaros and Nikos Papadakis

Technological Educational Institute of Crete
Keynote Talk: Friday, 8 July, 2010, 09:30-10:30 am

"Multicores for low-power embedded systems and high performance computing"
Prof. Ioannis Papaefstathiou
Technical University of Crete

As it is widely known Moore's Law has reached the point at which we can build single-chips with large numbers of processor cores and significant amounts of memory. Multiprocessor systems-on-chips (MPSoCs) have opened up new application areas including low-power and real-time embedded systems as well as high-end computing systems. This talk will review the architectures of multiprocessor systems-on-chips and the design methodologies utilized in developing them. MPSoCs make use of advanced processors, memory systems, and on-chip networks, while the design methodologies required designing these complex systems are built on top of earlier such design tools but they also address many new design challenges.

Prof. Ioannis Papaefstathiou is an elected Associate Professor at the Department of Electronic and Computer Engineering at the Technical University of Crete and a Senior Researcher at the Telecommunication Systems Institute. He is working in the design and implementation methodologies for networking systems with tightly coupled design parameters and highly constrained resources. He was granted a PhD degree in computer science at the University of Cambridge UK, in 2001, an M.Sc. degree (Ranked 1st) from Harvard University, Cambridge, MA, in 1996 and a B.Sc. degree  from the University of Crete, Greece in 1996.  From 1994-1996 he was a VLSI systems engineer at ICS-FORTH, and from 1997-2000 he was a Research Associate at the Systems Research Group, Computer Laboratory, University of Cambridge. From 2001-2005 he was the manager of the Crete R&D department of Ellemedia Technologies, a closely affiliated to Lucent’s Bell Labs microelectronics company. He has published more than 40 papers in IEEE-sponsored journals and conferences.  He has been the prime Guest Editor for an issue of IEEE Micro Magazine and he has served as a scientific evaluator for the Commission of the European Communities (FP6 and FP7-IST), as well as for the Greek General Secretariat for Research and Technology. He has participated in many European R&D Programmes, ACTS, ESPRIT, IST and he is a member of IEEE.


Invited Talks: Friday, 9 July, 2010, 09:30-10:30 am

“Programming in the multicore era"
Dr. Kornilios Kourtis
National Technical University of Athens

Up until a few years ago, parallel programming was a dark, esoteric art, performed by a small number of specialists to satisfy high-performance requirements. In recent years, however, architects have hit hard limits and are unable to boost serial CPU performance. Instead, they have turned to multicore designs making parallel architectures ubiquitous. As a result, one of the major computing challenges of our time is the adaptation of software to the paradigm of parallel programming. We consider three different goals for parallel programming: performance, productivity and generality. This talk will briefly present the most dominant parallel programming models and discuss their trade-offs regarding the three aforementioned goals.

Antonios - Kornilios Kourtis received his Diploma in Electrical Engineering in 2004 from the National Technical University of Athens. In 2010, he received his Ph.D. degree from the School of Electrical and Computer Engineering of the same institution. Dissertation title: Data compression techniques for improving the performance of memory-intensive applications on shared memory architectures. His current research interests are focused on Parallel Programming, High Performance Computing, and Operating Systems. He has teaching assistant experience in several undergraduate courses. He was also a reviewer for several conferences of IEEE/ACM and he is a member of the IEEE Computer Society.


















“Multicore SoCs and Virtual Platforms"
Efstratios Politis
ISD S.A.

Multicore SoC evolution requires Network-on-Chip (NoC) as a breakthrough technology that provides communication services through a simple, structured, scalable and efficient on-chip network infrastructure based on communication links, on-chip routers and network interfaces that implement appropriate adaptation layers.
In this talk, we describe involvement in system-level SoC/NoC design through recent European R&D projects. These projects focus on multicore SoC/NoC design libraries and languages, NoC design, high-level power estimation, and power-efficient integration of hybrid multicore programming paradigms and fault tolerance mechanisms.

Efstratios Politis received his BSc in Computing Science from the University of Newcastle (1991) and his MSc in Advanced Computer Systems from the University of Edinburgh (2000). Since 2002, Efstratios has been employed at ISD S.A. He has working experience in a wide range of activities, including embedded operating system development for consumer electronic SoCs, system-level modeling with SystemC, and design and development of a distributed e-Health platform. In addition, he has participated in validation of a micro-controller on behalf of the European Space Agency and several European Union R&D projects on system-level modeling, multicore programming, power estimation and reliability.















Venue Information:

The conference venue is the Galaxy Hotel, a sophisticated, superior first-class hotel conveniently located in Heraclion's most elegant business and leisure district (south east corner on the map below), offering ideal hospitality for business and leisure travellers.

Links to clickable maps are included in the website.


8th Workshop on Intelligent Solutions on Embedded Systems
(WISES 2010)

Galaxy Hotel, Heraklion, Crete, Greece
8-9 July 2010

http://wises2010.cs.teicrete.gr

Program Schedule
Thursday, July 8, 2010
Room - Ballroom
08:30 –09:00
Registration
09:15 – 09:30
Opening Session

Welcome by General Chairs and Program Co-Chair
M. Grammatikakis,  G. Kornaros, N. Papadakis
Technological Educational Institute of Crete
09:30 –10:30
Keynote Talk

Multicores for low-power embedded systems and high performance computing

Prof. Ioannis Papaefstathiou,
Department of Electronic & Computer Engineering
Technical University of Crete

10:30 – 11:00
Break
11:00 – 12:15
Session 1: Architectural Level Techniques in Embedded Systems
Chair: Natividad Martínez Madrid

P1.1     Algorithm acceleration on LEON-2 processor using a     Reconfigurable Bit Manipulation Unit
G.C. Cardarilli, L. Di Nunzio, R. Fazzolari, M. Re
University of Rome Tor Vergata, Italy

P1.2     SES-based Framework for Fault-tolerant Systems
Michael Steindl, Juergen Mottok, Hans Meier
University of Applied Sciences Regensburg, Germany

P1.3    Hardware Support for Dynamic Scheduling in Multiprocessor     Operating System
Bhuvana Kakunoori, Sreekumar Choya Madathil
DS India Labs, Samsung India Software Operations, India
12:15 –  13:30
Lunch Break: Restaurant Vetri
14:00 – 15:15
Session 2: Smart Sensor Platform Applications
Chair: Massimo Conti

P2.1     Sensors in Trading Process: A Stress – Aware Trader
Javier Martinez Fernandez*, Juan Carlos Augusto†, Ralf Seepold**,     Natividad Martínez Madrid*
*University Carlos III of Madrid, Spain
†University of Ulster, Northern Ireland
**University of Applied Sciences, Konstanz, Germany

P2.2     Opening information of low capacity embedded systems for     Smart Spaces
Jussi Kiljander,  Matti Etelapera, Janne Takalo-Mattila,  Juha-Pekka     Soininen
VTT Technical Research Centre of Finland

P2.3     A gateway-based solution for remote accessing to residential     UPnP services networks
Jesus Saez Gomez-Escalonilla*, Julio Angel Cano Romero*, Ralf     Seepold**,     Natividad Martinez Madrid*
*University Carlos III of Madrid, Spain
**University of Applied Sciences, Konstanz, Germany

15:15 –15:45
Break
15:45 – 17:00
Session 3: Advances in Embedded Software Verification and Development
Chair: G.C. Cardarilli and Luca Di Nunzio

P3.1     Verification of Behavioral Compatibility in the Virtual     Integration Methodology     
Michael Schrorer*, Stefan Kuntz†, Juergen Mottok*
*University of Applied Sciences, Regensburg, Germany
†Continental Automotive GmbH, Germany

P3.2     A Comprehensive Development Guide for Network Embedded     Systems
Apostolos N. Meliones
University of Piraeus, Greece

P3.2     Using a Prioritized MAC Protocol to Execute the Database     Operation Join in Networked Embedded Computer Systems
Bjorn Andersson, Nuno Peira, Eduardo Tovar,  Filipe Pacheco
Polytechnic Institute of Porto
19:00
Depart for Dinner Banquet
19:30
Dinner
0:00
Return

Friday, July 9, 2010
Room - Ballroom
9:00-10:15
Invited Talks

Programming in the multicore era
Dr. Nikos Anastopoulos
Department of Electrical and Computer Engineering
National Technical University of Athens


Multicore SoCs and Virtual Platforms
Stratos Politis
ISD SA
10:15 – 10:45
Break
10:45 – 12:00
Session 4: Embedded Prototype Applications
Chair: Ralf Seepold

P4.1     Performance analysis of JPEG 2000 over 802.15.4 wireless     image sensor network
Pieretti Andrea, Christiano Scavongelli, Simone Orcioni, Massimo Conti
Università Politecnica delle Marche, Italy

P4.2     From C to VM-targeted Executables: Techniques for     Heterogeneous Sensor/Actuator Networks
Aleksander Pruszkowski, Tomasz Paczesny, Jaroslaw Domaszewicz
Warsaw University of Technology (WUT), Poland

P4.3     A Novel Command Generation Method with Variable Feedrate     utilizing FGPA for Motor Drives
Ulas Yaman, Melik Dolen , A. Bugra Koku
Middle East Technical University, Turkey

12:15– 14:00
Lunch Break: Restaurant Vetri
14:00 – 15:15
Session 5: Analogue and Mixed-Signal Implementations
Chair:  Andreas Koenig
P5.1     Selecting Appropriate Calibration Points for an Ultra Low Area     8-bit Subrange ADC
Nikos Petrelis, Michael Birbas, John Kikidis, Alexios Birbas
Analogies S.A., Greece

P5.2     DC-AC Power Converter using Sigma-Delta Modulation
Rocco D. d Aparo, Giorgio Crostella, Davide Nicoletti, Simone Orcioni,     Massimo Conti
Università Politecnica delle Marche, Italy

P5.3     Design Refinement for the Development of an Audio Dynamic     Range Controller
A.De Stephanis*,  M. Conti*, M. Caldari†, F. Ripa†
*Università Politecnica delle Marche, Italy
†KORG Italy S.p.A., Italy

15:15 – 15:45
Break
15:45 – 17:00
Session 6:
Chair: Juergen Mottok

P6.1     Minimizing Power Consumption in Wireless Sensor Networks     by Duty-Cycled Reconfigurable Sensor Electronics: A Case     Study for an AMR-Sensor Based Localization Approach
Kai Lutz, Andreas Konig
Institute of Integrated Sensor Systems, Kaiserslautern, Germany

P6.2     Current Characterisation for Ultra Low Power Wireless Body     Area Networks
Fabio Di Franco, Christos Tachtatzis, Ben Graham, Marek Bykowski, David     C. Tracey, Nick F. Timmons, Jim Morrison
Letterkenny Institute of Technology, Ireland

P6.3     Development and Implementation of a Network Processor     Architecture in Reconfigurable Logic (FPGA)
Constantinos Stefanatos*, Ioannis Papaefstathiou*,  Charalampos     Manifavas†
*Technical University of Crete, Greece
†Technological Educational Institute of Crete, Greece


WISES2010 Best Paper Award
17:15 - 17:30
Closing



Saturday, July 10, 2010
Visit to Knosos

9:00-11:00    A visit to Knossos and a tour by Gareth Owens (http://en.wikipedia.org/wiki/Gareth_Alun_Owens), Associate Director and «Erasmus/Socrates» Manager/Tutor of the International Relations Office, TEI of Crete and Associate Professor of Hellenic Culture - History, Language and Civilization. The Palace of Knossos is the largest of the preserved Minoan palatial centers.
Thursday, July 8, 2010
Room - Ballroom

08:30 –09:00
Registration

09:15 – 09:30
Opening Session
Welcome

09:30 –10:30
Keynote Talk
Multicores for low-power embedded systems and high performance computing

10:30 – 11:00
Break



11:00 – 12:15
P1.1     Algorithm acceleration on LEON-2 processor using     a Reconfigurable Bit Manipulation Unit
P1.2     SES-based Framework for Fault-tolerant Systems
P1.3    Hardware Support for Dynamic Scheduling in     Multiprocessor Operating System

12:15 –  13:30
Lunch Break

14:00 – 15:15
P2.1     Sensors in Trading Process: A Stress – Aware     Trader
P2.2     Opening information of low capacity embedded     systems for Smart Spaces
P2.3     A gateway-based solution for remote accessing to     residential UPnP services networks

15:15 –15:45
Break

15:45 – 17:00
P3.1     Verification of Behavioral Compatibility in the Virtual     Integration Methodology     
P3.2     A Comprehensive Development Guide for Network     Embedded Systems
P3.2     Using a Prioritized MAC Protocol to Execute the     Database Operation Join in Networked Embedded     Computer Systems

19:00
Depart for Dinner Banquet

19:30

Dinner

0:00
Return


Friday, July 9, 2010
Room - Ballroom

9:00-10:15
Invited Talks


Programming in the multicore era


Multicore SoCs and Virtual Platforms

10:15 – 10:45
Break

10:45 – 12:00
P4.1     Performance analysis of JPEG 2000 over 802.15.4     wireless image sensor network
P4.2     From C to VM-targeted Executables: Techniques     for Heterogeneous Sensor/Actuator Networks
P4.3     A Novel Command Generation Method with     Variable Feedrate utilizing FGPA for Motor Drives

12:15– 14:00
Lunch Break

14:00 – 15:15
P5.1     Selecting Appropriate Calibration Points for an     Ultra Low Area 8-bit Subrange ADC
P5.2     DC-AC Power Converter using Sigma-Delta     Modulation
P5.3     Design Refinement for the Development of an     Audio Dynamic Range Controller

15:15 – 15:45
Break

15:45 – 17:00
P6.1     Minimizing Power Consumption in Wireless Sensor     Networks by Duty-Cycled Reconfigurable Sensor     Electronics: A Case Study for an AMR-Sensor     Based Localization Approach
P6.2     Current Characterisation for Ultra Low Power     Wireless Body Area Networks
P6.3     Development and Implementation of a Network     Processor Architecture in Reconfigurable Logic     (FPGA)


WISES2010 Best Paper Award

17:15
Closing